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  • 可重配置計算:體系結構與應用(ARC 2006 第2屆國際研討會論文集) - 書籍詳細信息
  • 查看同類圖書:科學技術»計算機/網絡»計算機科學理論與基礎知識»可重配置計算:體系結構與應用(ARC 2006 第2屆國際研討會論文集)
  • 可重配置計算:體系結構與應用(ARC 2006 第2屆國際研討會論文集)

  • 【作 者】:Koen Bertels
  • 【又/譯名】:LNCS-3985: Reconfigurable computing
  • 【叢編項】:
  • 【裝幀項】:平裝 / 468
  • 【出版項】:湖北辭書出版社 / 2006-12-1
  • 【ISBN號】:9783540367086 / 354036708X
  • 【原書定價】:¥678.00 有1家書店打折銷售 
  • 【主題詞】:計算機/網絡-計算機理論
  • 【圖書簡介】
      This book constitutes the thoroughly refereed post-proceedings of the Second International Workshop on Reconfigurable Computing, ARC 2006, held in Delft, The Netherlands, in March 2006.The 22 revised full papers and 35 revised short papers presented were thoroughly reviewed and selected from 95 submissions. The papers are organized in topical sections on applications, power, image processing, organization and architecture, networks and communication, security, and tools.
  • 【本書目錄】
    Applications
    Implementation of Realtime and Highspeed Phase Detector on FPGA
     Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform
     Configurable Embedded Core for Controlling Electro-Mechanical Systems
     Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors
     Dynamic Partial Reconfigurable FIR Filter Design
     Event-Driven Simulation Engine for Spiking Neural Networks on a Chip
     Towards an Optimal Implementation of MLP in FPGA
    Power
     Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture
     Quality Driven Dynamic Low Power Reconfiguration of Handhelds
     An Efficient Estimation Method of Dynamic Power Dissipation on VLSI interconnects
    Image Processing
    Highly Paralellized Architecture for Image Motion Estimation
    Design Exploration of a Video Pre-processor for an FPGA Based SoC
     QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
     Applications of Small-Scale Reconfigurability to Graphics Processors
     An Embedded Multi-camera System for Simultaneous Localization and Mapping
     Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynanmcally Reconfigurable Processor
     Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip
     Handel-C Design Enhancement for FPGA-Based DV Decoder
     Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’Platform
     A New VLSI Architecture of Lifting-Based DWT
    ……
    Organization and Architecture
    Networks and Communication
    Security
    Tools
    Author Index
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